An integrated circuit packaged device generally includes an integrated circuit chip lying on a chip support pad. Wire bonds connect the IC to a lead frame. A substance, such as plastic, encapsulates the structure. The plastic small outline J lead (PSOJ) package is one exemplary example. For application, one technique uses reflow solder to surface mount the IC package to a printed circuit board.
As the industry moves towards thinner packages and packages containing chips of larger size for higher volumetric packaging, new packaging techniques are evolving. One such technique is the lead on chip package, (LOC). As described in U.S. Pat. No. 4,862,245 to Pashby et al., issued Aug. 29, 1989, and in U.S. Pat. No. 4,916,519 to Ward, issued Apr. 10, 1990, and in the article entitled Volume Production of Unique Plastic Surface Mount Modules For The IBM 80-ns 1-Mbit DRAM Chip by Area Wire Bond Techniques by William C. Ward, published at the 38th ECC in IEEE 1988, pages 552-557, this technique disposes a lead frame over the active area of an integrated circuit. Adhesive insulating tape attaches the lead frame to the integrated circuit chip. Wire bonds connect the circuit to the centrally disposed power supply busses. And, wire bonds jump over the power supply busses to connect the integrated circuit to conductive lead fingers. No chip support pad is required.
Concerns exist about potential wire bond shorting to the power bus portions of the lead frame in the LOC package. Since the wires to the signal pins cross the metal lead frame power bus, the opportunity for shorting may arise from assembly processes such as poor bond location, wire loop control, mold compound sweep, or from accidental touching during processing. These assembly process also create concerns about shorting between the wirebonds themselves.
One approach to minimize shorting problems suggests the use insulated wire. See, Insulated Aluminum Bonding Wire For High Lead Count Packaging by Alex J. Oto, International Journal For Hybrid Microelectronics, Vol. 9, No. 1, 1986. While insulated wire has been reported to have some degree of success in conventional assembly packages, the successful implementation in a LOC package is questionable due to the nature of the wire bond stitch as it occurs over the insulating film on top of the integrated circuit; the probability of successful implementation is therefore less likely. Additionally, insulated wire is expensive.
It is an object of this invention to provide a solution to wire bond shorting in lead on chip integrated circuit packaged devices.
Other objects and benefits of this invention will be apparent to those of ordinary skill in the art having the benefit of the description to follow herein.